The present invention relates generally to semiconductor fabrication, and more particularly to methods for improving the reliability of 0.25-xcexcm technology semiconductors by alleviating stress in interconnect lines that might otherwise result in the formation of voids in the interconnect lines.
Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
In chips that hold integrated circuits, the individual circuit components are interconnected by conductive elements referred to as xe2x80x9cinterconnect lines.xe2x80x9d These interconnect lines are typically arranged in a multi-layered pattern that is deposited on a semiconductive substrate such as silicon. To insulate the interconnect lines from each other, insulative material is deposited between adjacent interconnect line layers.
With the above in mind, so-called 0.25-micron technology has been developed, in which the distance between adjacent layers of interconnect lines in an integrated circuit on a semiconductor chip is equal to or less than about three-eighths of a micron. With such a small spacing between interconnect lines, which have heights of about 1.1 microns, the size of the circuits on the chip can be reduced to result in the above-noted advantages.
Typically, each electrically conductive interconnect line is made of a xe2x80x9cstackxe2x80x9d of metal layers that typically includes a layer made of aluminum or aluminum alloy, and one or more other metal layers. The aluminum is deposited as a film over the substrate and is then lithographically patterned and chemically etched to form a desired pattern for the circuit""s connector lines. Then, a process referred to as high density plasma (HDP) inter-layer dielectric (ILD) formation is used to fill the gaps between adjacent metal stacks with an electrically non-conductive material. Ordinarily, the ILD deposition step is undertaken at relatively high temperature, incidentally precipitating the formation of an intermetallic structure. In current applications, titanium is commonly used as an underlayer for the aluminum, and the intermetallic structure that forms in such a device is TiAl3. Also, an overlayer that includes TiN anti-reflective coating (ARC) is disposed over the stacks, for lithography purposes.
As understood herein, however, voids caused by hydrostatic stresses undesirably can form in the aluminum, and the voiding of the aluminum can be accelerated by the formation of the intermetallic structure. This is undesirable, because when a void forms in a thin aluminum line, the current path through the line unfortunately is diverted, thereby adversely affecting the reliability of the chip.
The present invention understands that the above-mentioned hydrostatic stresses arise because the thermal expansion coefficient of the aluminum layer is different from the thermal expansion coefficient of the encapsulating ILD and the silicon substrate, both of which mechanically constrain the aluminum. Furthermore, when an intermetallic structure such as TiAl3 is formed, the intermetallic structure can volumetrically contract (by 5.9%, in the case of TiAl3), and the aluminum in the intermetallic structure, which is the most compliant metal in the stack, will consequently absorb the contraction-induced strain and thus have an even higher stress state as a result. Additionally, we have discovered that the undesirable voiding can be accelerated by relatively high compressive stress caused by high silane volume flow rates of sixty six standard cubic meters per minute (66 SCCM) and higher and relatively high temperatures (caused by applying relatively high bias power of 3500 watts and higher) during ILD deposition.
Fortunately, the present invention recognizes that contrary to previous methods based on larger-geometry chips, in which pre-annealing interconnect lines prior to ILD deposition would have undesirably formed hillocks, i.e., extrusions of metal, in the chip structure, it is possible to anneal the metal stacks prior to ILD deposition in 0.25-xcexcm semiconductors, when only the substrate, and not the ILD, constrains the aluminum in the stacks. As recognized by the present invention, the consequence is that the likelihood of void formation in the interconnect lines is reduced, thereby improving 0.25-xcexcm chip reliability. The present invention moreover understands that relatively low temperatures and silane flow rates during ILD deposition can be used to further reduce the likelihood of void formation in the interconnect lines.
A method is disclosed for making a semiconductor chip having electrically conductive interconnect lines. The method includes providing at least one substrate, and establishing at least one predetermined pattern of electrically conductive interconnect lines on the substrate. In accordance with the present invention, prior to depositing a dielectric layer between the interconnect lines, the lines are annealed, and then the dielectric layer (ILD) is deposited from a source gas with a flow rate maintained at a volume flow rate of no more than sixty five standard cubic centimeters per minute (65 SCCM).
In a preferred embodiment, the substrate is disposed on a support, and a bias power of no more than three thousand four hundred (3400) watts is applied to the support. More preferably, the bias power is no more than 3000 watts. Further, when the source gas is silane, the particularly preferred volume flow rate of the source gas used to deposit the ILD is less than sixty standard cubic centimeters per minute (60 SCCM), and can be between forty (40) SCCM and 60 SCCM.
As intended by the present invention, each line establishes a stack including at least one layer having aluminum, and an alloy of titanium and aluminum is formed during the annealing step. As disclosed in detail below, the annealing step is undertaken by heating the electrically conductive lines to a temperature of between three hundred fifty degrees Celsius and four hundred fifty degrees Celsius (350xc2x0 C.-450xc2x0 C.) for a period of between ten minutes and ninety minutes. If desired, the ILD source gas can be silane or TEOS, and the ILD is deposited by directing the ILD source gas onto the lines while simultaneously removing excess ILD material by sputtering. A chip made according to the method, and a computing device incorporating the chip, are also disclosed.
In another aspect, a semiconductor chip includes at least one substrate and at least one predetermined pattern of aluminum lines supported by the substrate. Adjacent lines are separated by distances equal to or less than about three-eighths of a micron. An alloy of aluminum and titanium is formed on the lines, with the alloy being reacted prior to insulating the lines from each other. In accordance with the present invention, the lines are insulated from each other by vapor deposition of an inter layer dielectric (ILD) from a source gas at a volume flow rate of no more than sixty standard cubic centimeters per minute (60 SCCM).
In still another aspect, a method for making a semiconductor chip includes establishing plural electrically conductive lines on at least one substrate. The lines are spaced from each other by distances equal to or less than three-eighths of a micron. The method further includes depositing a dielectric between at least two lines that are adjacent each other using a source gas at a volume flow rate of no more than sixty five standard cubic centimeters per minute (65 SCCM).
Other features of the present invention are disclosed or apparent in the section entitled: xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d